1. Field of the Invention
One area in which local conditions affect the behavior of active elements of an integrated circuit is leakage current. The transistors used in certain types of state-of-the-art integrated circuits are inherently "leaky", i.e., even when the transistor is turned off, there is a flow of current from source to drain. As feature size decreases and circuit complexity increases, leakage curent when a transistor is off becomes both more important and more subject to local conditions. One class of integrated circuits in which leakage current has become an important problem is those which employ dynamic gates fabricated from CMOS FETs. Such integrated circuits are described in Chapter 5 of Masakazu Shoji, CMOS Digital Circuit Technology, Prentice-Hall, Englewood Cliffs, N.J. 1988 (henceforth "Shoji"). In CMOS FETs, the problems posed by the inherent leakage current increase as the feature size decreases and the complexity of the circuit increases for the following reasons:
As the size of a CMOS FET decreases, its threshold voltage generally decreases, either because power supply voltage is decreased or the design requires the higher performance possible with lower threshold voltages. As the threshold voltage decreases, the leakage current increases exponentially. PA1 As the complexity of the system constructed in a single integrated circuit increases, more complex logic gates are required to process signals efficiently and there may be as many as several hundred FETs connected to a node. As the number of FETs connected to a node increases, the difference between the leakage current in the node and the current which flows when only one of the FETs is on decreases. PA1 As the device number increases and the device size decreases, local variations in device geometry, in temperature, and in electrostatically induced noise increasingly influence the leakage current through a given FET. PA1 NFETs 105, 117, and 119 implement the NOR function. PA1 PFET 103 precharges output node 111. PA1 NFET 115 is a ground switch. When it is on, it grounds the source electrodes of NFETs 105, 117, and 119. PA1 PFET 107 is a usually small FET which compensates for leakage current through NFETs 105, 117, and 119 when those FETs are off. PA1 A given NFET may be located at some distance from PFET 107 and, as a consequence of imperfections in the process which produces the integrated circuit, may have an I.sub.L greater or less than what was specified. PA1 The given NFET may be in a location in the integrated circuit which is warmer or cooler than the location of PFET 107, again producing I.sub.L greater or less than what was specified. PA1 The given NFET may be in a location in the integrated circuit where gate capacitance is greater or lesser than at the location of PFET 107. Since gate capacitance of a FET is related to its leakage current, the effect is to again produce I.sub.L greater or less than specified. PA1 a detecting element in the portion which is subject to the local condition and produces a response thereto which is proportional to the effect of the local condition on the active element; and PA1 compensation means connected to the detecting element and to the portion for reacting to the response of the detecting element to the local condition by providing a compensating input to the portion which is proportional to the response and which compensates for the effect of the local condition on the active element. PA1 a leakage current determination component which is incorporated into the portion of the integrated circuit and which has a second leakage current which is proportional to and varies with the first leakage current and PA1 a compensating current providing component which is connected to the leakage current determination means and to the portion and which receives the second leakage current and responds to the second leakage current by producing a compensating current substantially equal to the first leakage current and providing the compensating current to the portion.
For all of the above reasons, the inherent leakage of CMOS FETs is regarded by those skilled in the art as a limitation on the use of CMOS FETs in certain very large integrated circuits such as dynamic programmable logic arrays (PLAs) and dynamic memories.
2. Description of the Prior Art
FIG. 1 shows a prior-art solution to leakage current in dynamic CMOS gates. Circuit 101 is taken from page 213 of Shoji. It implements a three-input NOR gate. The inputs to the NOR gate are labeled A, B, and C, and the output is labeled O. The circuit is made of two kinds of CMOS field-effect transistors (FETs). FETs 103 and 107 are PFETs; the remaining FETs are NFETs. The functional difference between the two types is that a PFET conducts when its gate is at a low voltage, while a NFET conducts when its gate is at a high voltage. The FETs in circuit 101 have the following functions:
Operation of circuit 101 is controlled by clock signal 113. When clock 113 is low, PFET 103 is on and NFET 115 is off; as a consequence, line 111 is precharged to V.sub.DD. When clock 113 goes high, PFET 103 is off and NFET 115 is on; consequently, if any of NFETs 105, 117, or 119 is on, i.e., if any of lines A, B, or C has a logic high value, output line 111 is grounded; if none of lines A, B, or C has a logic high value, output line 111 remains at V.sub.DD to which it was precharged. The relationship between the states of lines A, B, and C and that of output line O 111 is thus that of the logic NOR function.
As indicated above, there is a leakage current through NFETs 105, 117, and 119 when those FETs are off. The gate of PFET 107 is grounded, and consequently that PFET is always on; PFET 107 is sized such that the flow of current through PFET 107 is on the one hand able to compensate for the leakage of current through NFETs 105, 117, and 119 when NFETs 105, 117, and 119 are all off and is on the other hand small enough so that output line 111 is close to ground potential when one or more of NFETs 105, 117 and 119 is on.
PFET 107's compensation for the leakage currents through NFETs 105, 117, and 119 comes at a cost. Because it is impossible to closely estimate the leakage current of NFETs 105, 117, and 119 when the integrated circuit is designed, PFET 107 is always designed to supply more current than the actual leakage current; consequently, when one of NFETs 105, 117, and 119 is on, output line 111 does not go completely to ground. If, as in the case of CMOS PLAs, output line 111 is an input for another gate, the logical behavior and the noise sensitivity of that gate may be affected by the fact that output line 111 does not go completely to ground.
The problems posed by PFET 107 increase as feature size decreases and circuit complexity increases. First, as threshold voltages decrease, a dynamic CMOS gate which takes output line 111 as an input becomes more sensitive to the fact that output line 111 is not at ground when one of NFETs 105, 117, and 119 is on. One consequence of this sensitivity is an increase in leakage current in that CMOS gate. Second, as leakage current increases and the number of FETs connected to a node increases, the difference between the total leakage current and the current resulting from any one of NFETs 105, 117, and 119 being on decreases. The leakage current for a node with n NFETs connected to it is n.multidot.I.sub.L. If the node is to function satisfactorily as a logical device, the current I.sub.O which results when only one of the NFETs connected to the node is on must be substantially greater than n.multidot.I.sub.L. Third, as the density of the integrated circuit and its speed increase, the noise in the circuit increases and the leakage current increases proportional to the exponential of the noise voltage. Finally, as the number of devices increase, the effects of locality also increase. For example:
Thus, as circuit speed, density, and complexity increase and n.multidot.I.sub.L and I.sub.O approach each other, a current source such as PFET 107 which provides a fixed current flow becomes more and more unsatisfactory. What the art requires, and what is provided by the apparatus disclosed herein, is an integrated circuit in which compensation for effects caused by local conditions (in this case, the leakage current), is exactly proportional to the effect being compensated for.